Flyback Turns Ratio and Reflected Voltage — Chapter 6

Chapter 5 established the flyback energy-per-cycle requirement, magnetizing-inductance target, and primary-current waveform. Chapter 6 now selects the reflected voltage and primary-to-secondary turns ratio that connect those current-and-energy targets to duty cycle, demagnetization time, semiconductor stress, secondary current, and realizable winding turns.

By the end of this chapter, you should be able to define a consistent turns-ratio convention; calculate reflected output voltage; apply the correct DCM, BCM, and CCM volt-second relationships; evaluate MOSFET and rectifier stress; estimate demagnetization time and secondary current; select auxiliary turns; and prepare the ratio-and-voltage design brief needed for Chapter 7.

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Chapter 5 — Energy Storage, Magnetizing Inductance, and Peak Current

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Chapter 7 — Primary Turns, Secondary Turns, and Flux Density

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DESIGN ASSUMPTION — IDEALIZED PRIMARY-REFERRED VOLTAGE MODEL

Unless stated otherwise, this chapter defines the primary-to-secondary turns ratio as n = NP/NS. Reflected voltage is referred to the primary winding during the secondary conduction interval.

First-pass equations neglect leakage-inductance overshoot, clamp dynamics, winding resistance, rectifier dynamic behavior, resonant dead time, and controller-specific timing unless those effects are being discussed explicitly. The chapter produces a ratio-and-voltage design target—not final integer turns or a released transformer.

1. Turns Ratio and Reflected Voltage Form One Converter-Level Decision

Flyback turns ratio is not selected from input voltage and output voltage alone. It determines how the output voltage is reflected to the primary side and therefore changes the timing, current, and voltage stress of the complete converter.

Design QuantityHow Turns Ratio or Reflected Voltage Affects ItWhy It Must Be Rechecked
Reflected voltage, VRSets the primary-referred secondary voltage during energy delivery.It establishes demagnetization slope and contributes directly to MOSFET drain stress.
Primary duty cycle, DInteracts with input voltage and secondary conduction time through volt-second balance.The controller must retain regulation, reset, and timing margin across line and load.
MOSFET voltage stressHigher reflected voltage raises the drain plateau before leakage overshoot.Device rating, clamp voltage, transients, and derating must remain acceptable.
Secondary rectifier stressA larger primary-to-secondary ratio generally reduces input voltage reflected to the secondary.Reverse-voltage rating and ringing margin must remain adequate.
Secondary peak currentCurrent is transformed inversely to turns; larger NP/NS increases secondary current for the same primary current.Conductor, rectifier, RMS loss, and termination requirements change.
Demagnetization timeHigher reflected voltage removes magnetizing current more rapidly.DCM zero-current interval, BCM boundary, or CCM residual current must match the intended mode.
Integer winding turnsThe electrical ratio must be realized with whole primary and secondary turns.Rounding changes the actual reflected voltage and every related stress calculation.

A ratio that improves one constraint can worsen another. The design process should therefore select a reflected-voltage range first, translate it into a turns-ratio target, choose realizable integer turns in Chapter 7, and then return the actual ratio to the converter calculations.

SolidMag Engineering Insight

Turns Ratio Is a Stress, Timing, Current, and Winding Decision

The flyback transformer ratio simultaneously affects MOSFET voltage, rectifier voltage, demagnetization time, secondary current, duty cycle, winding turns, leakage behavior, and regulation.

The best ratio is not the ratio that makes one equation convenient. It is the ratio that creates an acceptable complete operating window after real integer turns, tolerances, parasitics, and protection margins are included.

2. Define the Turns-Ratio Convention and Winding Polarity

A flyback design can become confusing quickly if different documents use reciprocal turns-ratio definitions. This chapter uses the primary-to-secondary convention:

n=NPNSn=\frac{N_P}{N_S}

where NP is primary turns and NS is secondary turns. With this convention, a value of n = 8 means that the primary has eight times as many turns as the secondary.

ConventionDefinitionEffect on Equations
Primary-to-secondaryn = NP/NSReflected output voltage is multiplied by n; secondary current is approximately multiplied by n relative to primary current.
Secondary-to-primarynSP = NS/NPEvery ratio term is the reciprocal of the convention used in this chapter.
Auxiliary-to-secondaryNA/NSUseful for estimating auxiliary voltage from the regulated secondary during the OFF interval.

The winding-dot convention establishes instantaneous voltage polarity. During the primary switch ON interval, the secondary rectifier should be reverse biased. When the switch turns OFF, winding voltages reverse and the secondary rectifier should become forward biased.

Flyback transformer winding-polarity diagram showing an 8:1 turns ratio, MOSFET on and off states, secondary diode conduction, and 100.8 V reflected to the primary.

Figure 6-1. Flyback winding polarity and primary-referred reflected voltage during the energy-storage and energy-delivery intervals.

ENGINEERING CAUTION — STATE THE RATIO CONVENTION ON EVERY DESIGN

A turns ratio written only as “8:1” is ambiguous unless the winding order is stated. A reciprocal-ratio mistake can reverse current and voltage calculations by a large factor.

Use explicit labels such as NP:NS = 8:1 and document winding dots, starts, finishes, and terminal assignments on the transformer drawing.

3. How Output Voltage Is Reflected to the Primary

During the MOSFET OFF interval, the output voltage, rectifier drop, and other secondary-side series drops appear across the secondary winding. The turns ratio reflects that voltage to the primary winding.

VR=n(VO+VD)V_R=n\left(V_O+V_D\right)

For a more detailed first-pass model that includes the secondary winding and connection drop:

VR=n(VO+VD+VW,S)V_R=n\left(V_O+V_D+V_{W,S}\right)

where VW,S represents the applicable secondary winding, lead, and connection voltage drop during energy delivery.

Solving for the required turns ratio:

n=VRVO+VDn=\frac{V_R}{V_O+V_D}

or, with the additional series drop included:

n=VRVO+VD+VW,Sn=\frac{V_R}{V_O+V_D+V_{W,S}}

The reflected voltage is not an independent physical source. It is the secondary conduction voltage expressed on the primary side through the transformer ratio. It appears on the primary drain-voltage plateau during the energy-delivery interval.

For multiple outputs, each secondary can imply a different reflected voltage because diode drops, winding resistance, load, and cross-regulation differ. The main regulated or highest-power output is commonly used as the primary design reference, but all outputs must be checked.

SolidMag Engineering Insight

Reflected Voltage Is the Bridge Between the Output and the Primary Switch

Output voltage and rectifier drop become a primary-side voltage through the turns ratio. That reflected voltage resets the magnetizing current and adds directly to the MOSFET drain plateau.

Selecting reflected voltage therefore connects output design, winding ratio, timing, switch stress, rectifier stress, and clamp design in one decision.

4. Volt-Second Balance in DCM, BCM, and CCM

In steady-state operation, the positive primary volt-seconds applied during the ON interval must be balanced by the negative primary-referred volt-seconds during secondary conduction.

VP,ONtON=VRtSV_{P,ON}t_{ON}=V_R t_S

Define the primary duty cycle and secondary conduction fraction as:

D=tONTsD=\frac{t_{ON}}{T_s}
DS=tSTsD_S=\frac{t_S}{T_s}

The general idealized relationship is:

VP,OND=VRDSV_{P,ON}D=V_R D_S
DS=VP,ONDVRD_S=\frac{V_{P,ON}D}{V_R}

In DCM, a zero-current fraction remains after demagnetization:

D+DS+DZ=1D+D_S+D_Z=1
DZ=1−D−DSD_Z=1-D-D_S

Therefore, for a selected DCM zero-current target:

VR=VP,OND1−D−DZV_R=\frac{V_{P,ON}D}{1-D-D_Z}

At the boundary of conduction, the zero-current interval approaches zero:

DZ≈0D_Z\approx0
DS≈1−DD_S\approx1-D
VR≈VP,OND1−DV_R\approx\frac{V_{P,ON}D}{1-D}

The same first-order volt-second relationship applies in idealized CCM because the secondary conducts throughout the OFF interval, but the current waveform starts and ends at nonzero magnetizing current.

D≈VRVP,ON+VRD\approx\frac{V_R}{V_{P,ON}+V_R}
ModeSecondary Conduction FractionImportant Distinction
DCMDS < 1 − DA positive zero-current interval remains after demagnetization.
BCM / CrMDS ≈ 1 − DMagnetizing current reaches zero at approximately the next cycle boundary.
CCMDS = 1 − D in the idealized two-state modelResidual magnetizing current remains; power uses incremental stored energy rather than peak energy above zero.

ENGINEERING CAUTION — USE ACTUAL CONTROLLER TIMING

Quasi-resonant dead time, active-clamp intervals, synchronous-rectifier timing, burst operation, valley switching, and variable frequency can add intervals that are not represented by the idealized two-state equations.

Use the actual controller law and measured switching waveform when finalizing duty cycle, secondary conduction time, and demagnetization margin.

5. Selecting the Reflected-Voltage Target

The reflected-voltage target should be selected within a feasible window created by timing, MOSFET stress, rectifier stress, current, efficiency, and integer-turn constraints.

For DCM at a specified duty cycle, a positive zero-current interval requires:

VR>VP,OND1−DV_R>\frac{V_{P,ON}D}{1-D}

Equality corresponds to the idealized boundary condition. If a specific zero-current fraction is desired:

VR=VP,OND1−D−DZ,TARGETV_R=\frac{V_{P,ON}D}{1-D-D_{Z,TARGET}}

An upper reflected-voltage limit can be estimated from the allowed MOSFET drain-voltage budget:

VR,MAX≈VDS,DESIGN−VBUS,MAX−VSPIKE,BUDGETV_{R,MAX}\approx V_{DS,DESIGN}-V_{BUS,MAX}-V_{SPIKE,BUDGET}

A secondary rectifier voltage limit can create a minimum turns-ratio requirement:

nMIN≈VBUS,MAXVRRM,DESIGN−VOn_{MIN}\approx\frac{V_{BUS,MAX}}{V_{RRM,DESIGN}-V_O}

This expression is only meaningful when the denominator is positive and when ringing, diode dynamics, and required derating are treated separately.

Lower Reflected Voltage Tends TowardHigher Reflected Voltage Tends Toward
Lower MOSFET drain plateauHigher MOSFET drain plateau
Longer secondary demagnetization timeShorter secondary demagnetization time
Smaller primary-to-secondary turns ratioLarger primary-to-secondary turns ratio
Higher secondary rectifier reverse stress from reflected inputLower secondary rectifier reverse stress from reflected input
Lower transformed secondary peak current for the same primary currentHigher transformed secondary peak current for the same primary current
Greater risk of losing the DCM zero-current interval at high duty cycleGreater DCM timing margin
Potentially more clamp-voltage headroomLess clamp-voltage headroom
Flyback reflected-voltage tradeoff chart comparing turns ratio, reflected voltage, peak primary current, duty cycle, and MOSFET drain-voltage stress for a 12 V output design.

Figure 6-2. Reflected voltage trades MOSFET stress against demagnetization time, rectifier stress, secondary current, and DCM timing margin.

SolidMag Engineering Insight

Choose a Reflected-Voltage Window, Not a Single Convenient Number

A practical design first identifies the lowest reflected voltage that satisfies reset and operating-mode requirements, then the highest reflected voltage allowed by switch and clamp stress.

The final target should sit inside that window with tolerance, transient, integer-turn, and production margin—not directly on one of its boundaries.

6. MOSFET Drain Stress, Leakage Spike, and Clamp Margin

During secondary energy delivery, the idealized MOSFET drain plateau is approximately the maximum primary bus plus the reflected output voltage:

VDS,PLATEAU≈VBUS+VRV_{DS,PLATEAU}\approx V_{BUS}+V_R

The actual peak also includes leakage-inductance overshoot, ringing, and other parasitic effects:

VDS,PK≈VBUS+VR+VLK,PKV_{DS,PK}\approx V_{BUS}+V_R+V_{LK,PK}

A useful voltage-budget expression is:

VLK,BUDGET=VDS,DESIGN−VBUS,MAX−VRV_{LK,BUDGET}=V_{DS,DESIGN}-V_{BUS,MAX}-V_R

The selected clamp or snubber must keep the actual peak below the design limit across leakage tolerance, maximum current, bus transients, temperature, and component variation.

Leakage energy at turn-off is approximately:

ELK=12LLKIP,PK2E_{LK}=\frac{1}{2}L_{LK}I_{P,PK}^2

If a dissipative clamp absorbs approximately this energy every cycle, a first-order loss estimate is:

PLK≈12LLKIP,PK2fsP_{LK}\approx\frac{1}{2}L_{LK}I_{P,PK}^2f_s
Drain-Voltage ComponentOriginDesign Action
Maximum bus voltageRectified line, DC source, ripple, and transient condition.Use the highest credible operating and surge value defined by the system requirements.
Reflected voltageSecondary conduction voltage multiplied by NP/NS.Select with turns ratio and timing; include diode and winding drops where appropriate.
Leakage spikeEnergy in transformer leakage inductance and PCB loop inductance.Control through winding design, layout, clamp or snubber, and adequate voltage margin.
RingingResonance among leakage inductance, device capacitance, winding capacitance, and layout parasitics.Measure the prototype and apply damping or topology changes where required.

ENGINEERING CAUTION — DEVICE RATING IS NOT THE DESIGN TARGET

Do not allocate the entire MOSFET absolute-maximum voltage rating to normal operation. Derating, avalanche capability, repetitive stress, transients, temperature, production variation, and required lifetime must be considered.

The acceptable reflected voltage is the value that leaves a verified clamp and transient budget—not merely the value that keeps the ideal plateau below the data-sheet maximum.

7. Secondary Rectifier Reverse Voltage and Current Stress

During the primary ON interval, the input bus is reflected to the secondary with reverse polarity. A first-order estimate of secondary rectifier reverse voltage is:

VRRM,IDEAL≈VO+NSNPVBUS,MAXV_{RRM,IDEAL}\approx V_O+\frac{N_S}{N_P}V_{BUS,MAX}

Using the turns-ratio convention in this chapter:

VRRM,IDEAL≈VO+VBUS,MAXnV_{RRM,IDEAL}\approx V_O+\frac{V_{BUS,MAX}}{n}

The actual device must also withstand ringing, rectifier dynamic behavior, layout inductance, output overshoot, temperature, and required derating.

At idealized turn-off commutation, ampere-turn continuity gives the initial secondary current:

IS,PK≈nIP,PKI_{S,PK}\approx n I_{P,PK}

For an approximately triangular DCM secondary current that decays from peak to zero during DS:

IS,RMS≈IS,PKDS3I_{S,RMS}\approx I_{S,PK}\sqrt{\frac{D_S}{3}}

A larger primary-to-secondary ratio generally lowers rectifier reverse stress but raises secondary peak and RMS current. That tradeoff affects diode conduction loss, synchronous-rectifier sizing, conductor area, winding termination, and output-capacitor ripple current.

Turns-Ratio ChangeRectifier Voltage EffectSecondary Current Effect
Increase NP/NSReduces input voltage reflected to the secondary.Increases secondary current for the same primary current.
Decrease NP/NSIncreases input voltage reflected to the secondary.Reduces secondary current for the same primary current.

SolidMag Engineering Insight

Higher Reflected Voltage Moves Stress from Voltage Toward Current

Increasing the primary-to-secondary ratio can reduce secondary reverse-voltage stress and shorten demagnetization time, but the transformed secondary current rises.

The ratio should balance MOSFET voltage, rectifier voltage, secondary conduction loss, conductor geometry, output-capacitor ripple, and achievable winding turns.

8. Demagnetization Time and the Conduction-Mode Boundary

During the OFF interval, reflected voltage drives the primary-referred magnetizing current downward:

dIMdt≈−VRLm\frac{dI_M}{dt}\approx-\frac{V_R}{L_m}

For DCM or BCM, where current decays from IPK to approximately zero:

tS≈LmIPKVRt_S\approx\frac{L_m I_{PK}}{V_R}
DS=tSfsD_S=t_S f_s

Using volt-second balance, the same interval can be calculated from primary ON time:

tS=VP,ONtONVRt_S=\frac{V_{P,ON}t_{ON}}{V_R}

The remaining DCM zero-current interval is:

tZ=Ts−tON−tSt_Z=T_s-t_{ON}-t_S
DZ=1−D−DSD_Z=1-D-D_S

Higher reflected voltage steepens the demagnetization slope and shortens the secondary conduction interval. Lower reflected voltage lengthens energy delivery and can push an intended DCM design toward BCM or CCM at high duty cycle or heavy load.

Timing ResultInterpretation
DZ > 0DCM at the evaluated operating point.
DZ ≈ 0Boundary or critical conduction at the evaluated operating point.
Calculated DZ < 0The assumed current-starts-at-zero waveform is inconsistent; the converter enters CCM or the assumptions must change.

A controller may change frequency, duty cycle, peak current, burst behavior, or valley timing across line and load. The operating mode must be verified using actual timing, not only the nominal reflected voltage.

9. Current Transformation and Winding-Stress Tradeoffs

In the idealized magnetic circuit, primary and secondary ampere-turns are equal in magnitude during current commutation:

NPIP≈NSISN_P I_P\approx N_S I_S
IS≈NPNSIP=nIPI_S\approx\frac{N_P}{N_S}I_P=nI_P

The turns ratio therefore transforms voltage and current in opposite directions. A higher primary-to-secondary turns ratio raises reflected voltage and secondary current while lowering the input-derived reverse voltage on the secondary rectifier.

The current transformation influences:

  • Secondary conductor cross-sectional area and strand selection
  • Rectifier or synchronous-rectifier current rating
  • Output-capacitor RMS current
  • Winding termination and pin current
  • Copper loss and temperature rise
  • Leakage inductance and winding-layer geometry
  • Current sharing among multiple secondary windings

The ideal current step occurs through magnetizing coupling. Real leakage inductance and capacitance create a finite commutation interval and ringing, so measured peak current may differ from the instantaneous ideal transformation.

SolidMag Engineering Insight

Voltage Ratio Cannot Be Optimized Without the Current Ratio

A ratio chosen only to manage MOSFET or rectifier voltage can create an impractical secondary current, conductor, termination, or winding-window requirement.

Every reflected-voltage candidate should be checked with transformed peak current, RMS current, copper loss, window fill, and thermal performance before it is accepted.

10. Auxiliary Windings and Multiple Outputs

An auxiliary winding often powers a primary-side controller, senses the secondary voltage for primary-side regulation, or supplies an additional isolated output. Its turns should be calculated from the voltage present during the same secondary conduction interval.

NANS≈VA+VD,AVO+VD\frac{N_A}{N_S}\approx\frac{V_A+V_{D,A}}{V_O+V_D}
NA,IDEAL≈NSVA+VD,AVO+VDN_{A,IDEAL}\approx N_S\frac{V_A+V_{D,A}}{V_O+V_D}

After selecting integer auxiliary turns, the first-order realized voltage is:

VA,IDEAL≈NANS(VO+VD)−VD,AV_{A,IDEAL}\approx\frac{N_A}{N_S}\left(V_O+V_D\right)-V_{D,A}

This relationship is only a starting point. Actual auxiliary voltage is affected by:

  • Winding placement and coupling to the regulated output
  • Leakage inductance and ringing
  • Auxiliary load current and rectifier drop
  • Primary and secondary winding resistance
  • Cross-regulation among outputs
  • Sampling time in primary-side regulation
  • Burst and no-load operation
  • Integer-turn resolution

ENGINEERING CAUTION — DEFINE THE AUXILIARY REFERENCE DOMAIN

A primary-referenced controller-bias winding and a secondary-referenced isolated output are not interchangeable. Their insulation, pin placement, rectification, load behavior, and safety classification differ.

The requirements must state whether each auxiliary winding belongs to the primary circuit, secondary circuit, or another isolated domain before turns and winding order are finalized.

11. Integer Turns and the Realized Ratio

The electrical design produces an ideal ratio, but the transformer must be wound with whole turns. Absolute primary turns are selected in Chapter 7 from flux density, core area, material, frequency, and applied volt-seconds. Secondary turns are then derived from the target ratio:

NS,IDEAL=NPnTARGETN_{S,IDEAL}=\frac{N_P}{n_{TARGET}}

After choosing an integer secondary value:

nACT=NPNSn_{ACT}=\frac{N_P}{N_S}
VR,ACT=nACT(VO+VD)V_{R,ACT}=n_{ACT}\left(V_O+V_D\right)

The actual ratio must be returned to every converter calculation. Equivalent ratio families can have very different winding consequences. For example, 56:7, 64:8, 72:9, and 80:10 all produce an 8:1 ratio, but they differ in flux density, copper length, layer count, gap requirement, auxiliary-turn resolution, leakage, and capacitance.

Candidate TurnsRatioEngineering Consequence
56:78.000Fewest turns in this family; highest flux excursion for a given core area and applied volt-seconds.
64:88.000Intermediate turns and improved auxiliary-turn resolution.
72:98.000More copper length but convenient nine-turn secondary for some auxiliary ratios.
80:108.000Lowest flux excursion in this group but greater winding length and window use.

The ratio alone does not select the transformer. Chapter 7 must choose the absolute turns that satisfy flux, saturation, core loss, integer secondary turns, window fit, gap, and manufacturing constraints.

SolidMag Engineering Insight

Integer Turns Close the Converter-to-Transformer Loop

The theoretical turns ratio is a converter target. The integer primary, secondary, and auxiliary turns are the manufacturable transformer.

Once integer turns are selected, reflected voltage, timing, semiconductor stress, current, auxiliary voltage, and operating mode must all be recalculated using the realized ratio.

12. Worked Example — Selecting Reflected Voltage for the Chapter 5 Design

WORKED EXAMPLE — 100–375 V BUS TO 12 V / 5 A

This example continues the provisional Chapter 5 design. It assumes a 100 V minimum primary bus, 375 V maximum bus, 12 V / 5 A main output, 0.6 V main rectifier drop, 100 kHz switching frequency, 45% low-line duty cycle, 147.3 µH magnetizing inductance, and 3.06 A nominal peak primary current.

The target is fixed-frequency DCM at low line with approximately 10% of the switching period reserved as a zero-current interval. Leakage spike, clamp design, actual controller timing, flux, core, and absolute turns remain unresolved.

Input or TargetValue
Minimum primary bus100 V
Maximum primary bus375 V
Main output12 V / 5 A
Main rectifier drop0.6 V
Switching frequency100 kHz
Low-line duty cycle0.45
Target low-line zero-current fraction0.10
Magnetizing inductance147.3 µH
Nominal peak primary current3.06 A

Step 1 — Calculate the reflected voltage required for the target zero-current interval.

DS=1−D−DZD_S=1-D-D_Z
DS=1−0.45−0.10=0.45D_S=1-0.45-0.10=0.45
VR=VP,ONDDSV_R=\frac{V_{P,ON}D}{D_S}
VR=100(0.45)0.45=100 VV_R=\frac{100\left(0.45\right)}{0.45}=100\ \mathrm{V}

Step 2 — Calculate the ideal primary-to-secondary turns ratio.

nIDEAL=VRVO+VDn_{IDEAL}=\frac{V_R}{V_O+V_D}
nIDEAL=10012+0.6≈7.94n_{IDEAL}=\frac{100}{12+0.6}\approx7.94

Step 3 — Compare nearby reflected-voltage candidates.

Reflected VoltageIdeal RatioLow-Line Secondary FractionLow-Line Zero FractionHigh-Line Ideal Drain PlateauIdeal Rectifier Reverse VoltageSecondary Peak Current
80 V6.350.5625−0.0125 — inconsistent with the assumed DCM timing455 V71.1 V19.4 A
100 V7.940.45000.1000475 V59.3 V24.3 A
120 V9.520.37500.1750495 V51.4 V29.1 A

The 80 V candidate does not leave a zero-current interval at the stated 45% duty cycle. The 120 V candidate provides more timing margin and lower rectifier reverse stress, but raises MOSFET plateau voltage and secondary current. The provisional 100 V target provides the intended 10% zero-current interval before integer turns are selected.

Worked flyback reflected-voltage comparison showing 5:1, 8:1, and 11:1 turns ratios and their effects on reflected voltage, primary current, and MOSFET drain-voltage stress.

Figure 6-3. Comparison of 80 V, 100 V, and 120 V reflected-voltage candidates for timing, MOSFET stress, rectifier stress, and secondary current.

Step 4 — Select a provisional realizable ratio.

An 8:1 primary-to-secondary ratio is close to the ideal 7.94 value. The actual reflected voltage is:

VR,ACT=8(12+0.6)=100.8 VV_{R,ACT}=8\left(12+0.6\right)=100.8\ \mathrm{V}

Step 5 — Verify low-line DCM timing with the realized ratio.

DS=100(0.45)100.8≈0.4464D_S=\frac{100\left(0.45\right)}{100.8}\approx0.4464
DZ=1−0.45−0.4464≈0.1036D_Z=1-0.45-0.4464\approx0.1036

The realized 8:1 ratio leaves approximately 10.36% of the switching period as idealized zero-current time at the stated low-line operating point.

Step 6 — Estimate high-line duty and zero-current interval.

If the same magnetizing inductance, peak current, and switching frequency are maintained, the applied primary volt-seconds remain approximately constant:

VP,ON,LODLO≈VP,ON,HIDHIV_{P,ON,LO}D_{LO}\approx V_{P,ON,HI}D_{HI}
DHI≈100(0.45)375=0.12D_{HI}\approx\frac{100\left(0.45\right)}{375}=0.12
DZ,HI=1−0.12−0.4464≈0.4336D_{Z,HI}=1-0.12-0.4464\approx0.4336

This idealized fixed-frequency result shows a much longer zero-current interval at high line. The actual controller may alter frequency, peak current, burst behavior, or valley timing.

Step 7 — Estimate MOSFET drain plateau and voltage budget.

VDS,PLATEAU,MAX≈375+100.8=475.8 VV_{DS,PLATEAU,MAX}\approx375+100.8=475.8\ \mathrm{V}

A real MOSFET and clamp design must add leakage overshoot, ringing, bus transient, tolerance, and derating. If an illustrative internal drain-voltage design limit were 585 V, the remaining spike-and-clamp budget would be:

VLK,BUDGET=585−475.8=109.2 VV_{LK,BUDGET}=585-475.8=109.2\ \mathrm{V}

The 585 V limit is an example only; the actual limit must come from the selected semiconductor, reliability policy, and transient requirements.

Step 8 — Estimate secondary rectifier reverse stress.

VRRM,IDEAL≈12+3758=58.9 VV_{RRM,IDEAL}\approx12+\frac{375}{8}=58.9\ \mathrm{V}

Ringing, output overshoot, device dynamics, temperature, and derating must be added before selecting a rectifier.

Step 9 — Estimate secondary peak and RMS current.

IS,PK≈8(3.06)=24.48 AI_{S,PK}\approx8\left(3.06\right)=24.48\ \mathrm{A}
IS,RMS≈24.480.44643≈9.44 AI_{S,RMS}\approx24.48\sqrt{\frac{0.4464}{3}}\approx9.44\ \mathrm{A}

These idealized current values show why turns ratio cannot be selected from voltage stress alone. The secondary conductor, rectifier, output capacitor, terminations, and winding window must support the resulting pulsed current.

Step 10 — Identify candidate integer turns families.

The actual primary turns are not selected until Chapter 7. Candidate 8:1 families include 56:7, 64:8, 72:9, and 80:10. Each produces the same ratio but different flux, copper, gap, window, and auxiliary-turn consequences.

If a secondary-referenced 5 V auxiliary output with a 0.4 V rectifier drop were provisionally paired with a nine-turn main secondary:

NA,IDEAL≈95+0.412+0.6≈3.86N_{A,IDEAL}\approx9\frac{5+0.4}{12+0.6}\approx3.86

A provisional four-turn auxiliary would give:

VA,IDEAL≈49(12+0.6)−0.4≈5.2 VV_{A,IDEAL}\approx\frac{4}{9}\left(12+0.6\right)-0.4\approx5.2\ \mathrm{V}

This auxiliary example is valid only if the winding is secondary referenced and the stated diode-drop and load assumptions are appropriate.

First-Pass ResultValue
Selected reflected-voltage target100 V
Ideal primary-to-secondary ratio7.94:1
Provisional realizable ratio8:1
Actual reflected voltage100.8 V
Low-line secondary conduction fraction0.4464
Low-line zero-current fraction0.1036
High-line duty under stated constant-current assumptions0.12
High-line zero-current fraction0.4336
Maximum ideal drain plateau475.8 V
Ideal secondary rectifier reverse voltage58.9 V
Ideal secondary peak current24.48 A
Ideal secondary RMS current9.44 A

ENGINEERING CAUTION — THE 8:1 RATIO IS PROVISIONAL

Chapter 7 must determine the minimum primary turns from applied volt-seconds, core area, frequency, allowable flux excursion, material loss, and saturation margin. Only then can the final integer primary and secondary turns be selected.

After the actual turns are chosen, the reflected voltage, DCM timing, MOSFET stress, rectifier stress, secondary current, auxiliary voltage, and operating mode must be recalculated.

13. Design Handoff to Primary Turns, Secondary Turns, and Flux Density

Chapter 6 should end with a documented ratio-and-voltage design brief. Chapter 7 will convert that brief into absolute primary, secondary, and auxiliary turns using core area, applied volt-seconds, allowable flux density, material loss, integer-turn constraints, and winding fit.

Handoff ItemRequired Result
Turns-ratio conventionExplicitly state NP/NS and winding polarity.
Reflected-voltage targetNominal value and acceptable minimum/maximum range.
Input bus rangeMinimum and maximum primary voltage applied to stress and timing calculations.
Operating-mode timingDuty, secondary conduction fraction, zero-current interval, and frequency range at relevant corners.
MOSFET voltage budgetBus, reflected voltage, leakage/clamp budget, transient margin, and design limit.
Rectifier stressIdeal reverse voltage, ringing allowance, current, and derating requirement.
Current transformationPrimary peak current, secondary peak and RMS current, and output-capacitor implications.
Auxiliary requirementsReference domain, voltage, current, diode drop, regulation, and candidate ratio.
Integer-turn constraintsCandidate ratio families and required recalculation after Chapter 7 selects absolute turns.

SolidMag Engineering Insight

Reflected Voltage Defines the Operating Window; Absolute Turns Realize It

Chapter 6 selects the electrical ratio window that balances reset timing, MOSFET stress, rectifier stress, current, and auxiliary voltage.

Chapter 7 must now choose primary and secondary turns that realize that ratio while satisfying flux density, saturation, core loss, integer-turn resolution, gap, winding space, and manufacturability.

Technical references for this chapter include Texas Instruments guidance on DCM and CCM flyback design, Power Integrations design procedures for reflected output voltage, Infineon fixed-frequency flyback design guides, and STMicroelectronics quasi-resonant flyback documentation.

Related SolidMagnetics resources:

Chapter 5 — Energy Storage, Inductance, and Peak Current

Review the energy and current targets that feed the reflected-voltage calculation.

Transformer Turns Ratio Explained

Review the basic transformer voltage and turns-ratio relationship.

Complete Flyback Transformer Design Guide

Use the flagship guide for the full flyback design workflow and worked example.

Flyback Transformer Designer

Enter converter requirements and evaluate an automated flyback transformer design candidate.

Ready to Design a Flyback Transformer?

Move from design theory to an automated magnetic design. Enter the converter requirements and evaluate a coordinated transformer candidate, winding geometry, loss estimates, thermal performance, and CAD output.

Start Flyback Transformer Design →
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Chapter 5 — Energy Storage, Magnetizing Inductance, and Peak Current

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Chapter 7 — Primary Turns, Secondary Turns, and Flux Density

ABOUT THE AUTHOR

Stan Gibson

Electrical Engineer & Founder, SolidMagnetics

Stan Gibson is an electrical engineer and founder of SolidMagnetics, an engineering platform focused on magnetic-component design automation. His work includes power electronics, inductor and transformer design, magnetic-core selection, winding design, thermal analysis, and manufacturable CAD development. Through SolidMagnetics, he develops technical guides, calculators, and automated design tools intended to help engineers move from electrical requirements to practical magnetic-component designs.

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